The present invention is directed, in general, to a method of manufacturing a semiconductor device and, more specifically, to an improved method of manufacturing a vertical replacement gate (VRG) device wherein the channel length of the VRG is defined by implanting an epitaxial layer with an oxide and replacing the oxide with a gate material.
Enhancing semiconductor device performance continues to be a focus of the semiconductor industry. As a result, both smaller device size and increased performance have been identified as desirable manufacturing targets. As device dimensions within semiconductor devices, such as gates within integrated circuits (ICs), continue to shrink, the method for forming such gates has adapted to effectively accomplish the shrinking devices.
However, manufacturing limitations have particularly arisen with respect to the lithographic processes currently used to manufacture such smaller devices. In fact, current lithographic processes have been unable to accurately manufacture devices at the required minimal sizes. Moreover, this is a limitation that has presented a significant challenge to the semiconductor industry.
In view of the current limitations in the semiconductor manufacturing lithography process, and the desire to manufacture smaller devices, the semiconductor industry developed a vertical replacement gate (VRG) device structure, such as a VRG MOSFET. The VRG MOSFET structure circumvents the limitations associated with the lithographic process discussed above, by keeping each individual device component within functional lithographic limitations and building the devices vertically rather than horizontally on the semiconductor wafer. This allows overall device performance of the semiconductor wafer to be increased without encountering the lithographic limitations discussed above.
Unfortunately, conventional techniques commonly employed to form VRG devices are often process and labor intensive. At the outset of the manufacturing process, after a bottom source/drain layer has been implanted on a semiconductor wafer, several steps are still required before a trench can be etched. Specifically, the silicon wafer is placed in a first chamber where a bottom, doped layer, such as a p-type tetraethylorthosilicate (TEOS) layer, is first deposited or grown on the wafer. This first layer is deposited or grown using chemical vapor deposition (CVD). The layer is then planarized, perhaps with a chemical-mechanical planarization (CMP) process, before a second layer may be placed atop the first. After the CMP process, the wafer is taken to a different chamber where a second, sacrificial layer, usually comprising an oxide or nitride, is deposited or grown on top of the first layer. Then, as before, the wafer is taken back for the second layer to undergo the CMP process. The wafer is then taken back to the first chamber where an upper, doped TEOS layer is deposited or grown on top of the planarized sacrificial layer. Finally, the wafer is taken yet again to a CMP device where the third layer is planarized, so that an upper source/drain layer may eventually be deposited or grown on the planarized surface of this upper, doped TEOS layer.
In view of the foregoing, it is clear that common techniques for manufacturing a VRG device result in a time-consuming process. Moreover, these commonly used methods of manufacturing are also labor-intensive, with respect to both man and machine. As such, VRG manufacturing processes are often costly affairs, in spite of the advantages offered by VRG devices. With the already high cost of semiconductor manufacturing and a market already fraught with intense competition, manufacturers must make every effort to stream-line the manufacturing process.
Accordingly, what is needed in the art is an improved method of manufacturing a VRG device on a semiconductor wafer that does not suffer from the deficiencies of methods found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides an improved method of manufacturing a device. In one embodiment, the method includes depositing an epitaxial layer over a first source/drain region. A sacrificial layer is implanted within the epitaxial layer to preferably create first and second epitaxial layers. The thickness of the sacrificial layer substantially defines a channel length of the device. A trench is formed through the epitaxial layer and is filled with silicon to create a source/drain channel. The method may also include forming lightly doped drain regions on opposing sides of the source/drain channel. Gate oxides are also formed between the lightly doped drain regions. The sacrificial layer is removed and replaced with a gate layer. Other steps may include replacing the first and second epitaxial layers with first and second oxide layers and depositing a second source/drain region over the source/drain channel to thereby connect the first and second source/drain regions with the source/drain channel.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention are described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.